Energy efficient VLSI decoder chip with reduced PAPR in FECG monitoring

Medical data transmission is a major challenge in wireless communication to preserve their integrity and coherence. Orthogonal frequency division multiplexing (OFDM) has emerged as a modulation scheme that can achieve high data rates over frequency selective fading channel by multipath effects. As t...

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Bibliographic Details
Published in:International journal of electronics 2020-08, Vol.107 (8), p.1304-1323
Main Authors: Preethi, D, Valarmathi, R S, R, Harikumar
Format: Article
Language:English
Subjects:
Additive noises
Algorithms
Arrhythmia
Classifiers
Cockroach Swarm Optimisation
Computer simulation
Data recovery
Data transmission
decoder architectures
Discriminant analysis
Error correction
error predictionand correction adders
Integrated circuits
MIMO communication
Orthogonal Frequency Division Multiplexing
Peak to Average Power Ration
Power consumption
Selective fading
Signal processing
Wireless communications
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Summary:Medical data transmission is a major challenge in wireless communication to preserve their integrity and coherence. Orthogonal frequency division multiplexing (OFDM) has emerged as a modulation scheme that can achieve high data rates over frequency selective fading channel by multipath effects. As the foetal ECG (FECG) signal is large to process, the dimensionality of the data is reduced by linear discriminant analysis (LDA) and is then sent through the space time block coded (STBC) multiple input multiple output (MIMO) upon using cockroach swarm pptimisation algorithm as a classifier to demarcate the FECG signal from noise. This paper also proposes decoder design for STBC transmission over frequency-selective time-variant channels with data recovery at the receiver by using proposed error prediction and correction adders (EPD) to achieve reduced peak to average power ration (PAPR). The simulation results prove that the PAPR reduces by 1.3 dB and the sensitivity of classifier is 96.4%. The implementations are carried out over 200 data sets taken from MIT-BIH arrhythmia using simulation tools such as MATLAB 2013b, ModelSim 10.0b and Cadence Virtuoso under 65 nm. The finally fabricated and tested decoder chip consumes an average power of 0.64 µW.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207217.2020.1726490