Robust test generation for transistor stuck-open faults in CMOS complex gates

In this paper we give a new, systematic method to generate robust two-pattern test sets for transistor stuck-open (TSOP) faults in CMOS complex gates, using the Karnaugh map under a new approach. We consider CMOS complex gates consisting of transistor networks of either the sum of products (SP) or t...

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Bibliographic Details
Published in:International journal of electronics 1995-08, Vol.79 (2), p.129-142, Article 129
Main Authors: TSIATOUHAS, Y., PASCHALIS, A., NIKOLOS, D., HALATSIS, C.
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:In this paper we give a new, systematic method to generate robust two-pattern test sets for transistor stuck-open (TSOP) faults in CMOS complex gates, using the Karnaugh map under a new approach. We consider CMOS complex gates consisting of transistor networks of either the sum of products (SP) or the products of sum (PS) forms. Following the proposed method, all the unteslable TSOP faults are easily identified and the corresponding networks can be redesigned in order to become robustly testable. Our method is so simple and straightforward that it can be applied easily and quickly even in a manual processing way.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207219508926255