RF/Analog Performance of Novel Junctionless Vertical MOSFETs

In this paper, we analyze the radio frequency (RF) performance for novel junctionless vertical MOSFETs (JLVMOS) with different thicknesses of silicon pillar (T Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical s...

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Bibliographic Details
Published in:Integrated ferroelectrics 2011-01, Vol.129 (1), p.45-51
Main Authors: Tai, Chih-Hsuan, Lin, Jyi-Tsong, Eng, Yi-Chuen
Format: Article
Language:English
Subjects:
Analog
Numerical analysis
Performance evaluation
Radio frequency
Silicon
Transistors
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Summary:In this paper, we analyze the radio frequency (RF) performance for novel junctionless vertical MOSFETs (JLVMOS) with different thicknesses of silicon pillar (T Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical simulations, the JLVMOS of T Si = 5 nm gets the highest in g m and g m /I DS , but the T Si = 10 nm one gets the highest in A VI . Moreover, due to the double-gate (DG) structure of the VMOS, it can increase the gate controllability over the channel region.
ISSN:1058-4587
1607-8489
DOI:10.1080/10584587.2011.576899