Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

• Published in: Nanotechnology 2024-03, Vol.35 (10), p.105701
• Main Authors: Molina-Reyes, Joel, Cuellar-Juarez, Adriana Mercedes
• Format: Article
• Language: English
• Subjects: atomic-layer deposition; electron transport; high-k dielectric; MOSFET; Schottky barrier
• ISSN: 0957-4484; 1361-6528
• DOI: 10.1088/1361-6528/ad1161

By using a simple device architecture along with a simple process design and a low thermal-budget of a maximum of 100 °C for passivating metal/semiconductor interfaces, a Schottky barrier MOSFET device with a low subthreshold slope of 70 mV dec could be developed. This device is enabled after passivation of the metal/silicon interface (found at the source/drain regions) with ultra-thin SiO films, followed by the e-beam evaporation of high- quality aluminum and by using atomic-layer deposition for HfO as a gate oxide. All of these fabrication steps were designed in a sequential process so that a gate-last recipe could minimize the defect density at the aluminum/silicon and HfO /silicon interfaces, thus preserving the Schottky barrier height and ultimately, the outstanding performance of the transistor. This device is fully integrated into silicon after standard CMOS-compatible processing, so that it could be easily adopted into front-end-of-line or even in back-end-of-line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic.