A novel circular double-gate SOI MOSFET with raised source/drain

In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or to...

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Bibliographic Details
Published in:Semiconductor science and technology 2021-06, Vol.36 (6), p.65009
Main Authors: Kallepelli, Sagar, Maheshwaram, Satish
Format: Article
Language:English
Subjects:
circular double gate
circular single gate
drain induced barrier lowering
junctionless device
subthreshold slope
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Summary:In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or top and bottom (both). The results demonstrate that the best device configuration is a raised both CDGT with an internal pad as a drain. For the above configuration, the impact of a junctionless mode is further analyzed and the optimum performance is obtained with a doping level of 1 × 10 18 cm −3 . The device exhibits good electrical characteristics, with an ON/OFF current ratio of 3.73 × 10 5 , a near-ideal subthreshold slope of 66.9 mV dec −1 , and a small drain-induced barrier lowering of ∼35 mV V −1 . Among various circular MOSFETs, the CDGT device exhibits an optimum delay performance of 2 ps based on a two-stage inverter analysis.
ISSN:0268-1242
1361-6641
DOI:10.1088/1361-6641/abf0e6