Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and...

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Bibliographic Details
Published in:Semiconductor science and technology 2022-03, Vol.37 (3), p.35019
Main Authors: Lee, Sumi, Choi, Yejoo, Won, Sang Min, Son, Donghee, Baac, Hyoung Won, Shin, Changhwan
Format: Article
Language:English
Subjects:
CMOS inverter
complementary FET (CFET)
junctionless (JL) FET
junctionless accumulation mode (JAM) FET
metal ferroelectric insulator semiconductor (MFIS)
negative capacitance (NC)
self-heating effect (SHE)
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Summary:Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.
ISSN:0268-1242
1361-6641
DOI:10.1088/1361-6641/ac41e6