A junctionless dual-gate MOSFET-based programmable inverter for secured hardware applications using nitride charge trapping

• Published in: Semiconductor science and technology 2022-11, Vol.37 (11), p.115013
• Main Authors: Karmakar, Ananya, Mukherjee, Adrija, Dhar, Swastik, Sen, Dipanjan, Chanda, Manash
• Format: Article
• Language: English
• Subjects: charge trapping; CMOS inverter; junctionless dual gate MOSFET; programmability; secured hardware; short/long term plasticity; switching threshold
• ISSN: 0268-1242; 1361-6641
• DOI: 10.1088/1361-6641/ac92a3

In this paper we investigate a junction-less dual-gate metal–oxide–semiconductor field effect transistor (JL-DG-MOSFET)-based programmable inverter with an oxide–nitride–oxide (SiO 2 /Si 3 N 4 /SiO 2 ) gate stack, which offers short-/long-term memory as well as logic functionalities depending on charge trapping in the nitride layer. It has been shown that the pulsing interval plays a pivotal role in deciding the short-term plasticity/long-term plasticity window based on the charges trapped/detrapped at/near the oxide–nitride interface. Moreover, we have demonstrated a JL-DG-MOSFET-based complementary metal–oxide–semiconducor inverter with a programmable switching threshold and propose a scheme for secure key generation for authentication. The intra-Hamming distance among the 21 keys generated by the programmable inverter is also depicted to demonstrate the efficacy of the proposed framework. This will eliminate the physical separation between the logic and memory and can offer attractive solutions for silicon-based low-power neuromorphic computing and hardware security.