Effects of spacer layer thickness in InAlN/GaN double-channel HEMTs

• Published in: Semiconductor science and technology 2024-06, Vol.39 (6), p.65014
• Main Authors: Guo, Si-Yin, Zhu, Qing, Chen, Yi-Lin, Zhang, Meng, Mi, Min-Han, Zhu, Jie-Jie, Lei, Yi-Min, An, Si-Rui, Lu, Jia-Ni, Gong, Can, Ma, Xiao-Hua
• Format: Article
• Language: English
• Subjects: hysteresis phenomena; InAlN/GaN double-channel HEMT; trap; two-channel spacing
• ISSN: 0268-1242; 1361-6641
• DOI: 10.1088/1361-6641/ad4a2d

In this paper, the impact of upper channel layer thickness on the electrical characteristics and hysteresis behavior of double-channel InAlN/GaN HEMTs were investigated. The devices with an upper channel layer thickness of 20 nm exhibit higher output current and lower R on compared to devices with a thickness of 10/6 nm. This is attributed to the higher sheet carrier density and the reduced scattering. However, a 20 nm thickness of the upper channel layer in HEMT exhibits hysteresis phenomena in its electrical characteristics. For this hysteresis phenomenon, capacitance measurements and TEM characterization indicate that it is caused by dislocations in the lower barrier layer under the gate. A thicker upper channel layer is beneficial to increasing the output current of the device but leads to degradation of the lower InAlN barrier layer, resulting in hysteresis. This study provides an optimized solution for the growth and device fabrication of double-channel InAlN materials.