An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the dr...

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Bibliographic Details
Published in:Chinese physics B 2011-09, Vol.20 (9), p.392-395
Main Author: 周幸叶 张健 周致赜 张立宁 马晨月 吴文 赵巍 张兴
Format: Article
Language:English
Subjects:
Circuit design
Circuits
Computational efficiency
Computer simulation
Devices
Drains
HSPICE
Mathematical models
MOSFETs
Verilog-A
双栅MOSFET
电流模型
电路模拟器
电路设计
计算效率
设备模型
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Summary:As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.
ISSN:1674-1056
2058-3834
DOI:10.1088/1674-1056/20/9/097304