Back-side stress to ease p-MOSFET degradation on e-MRAM chips

The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal–oxide–silicon field-effect transistors, especially on p-type devices. Herein, a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress. Thro...

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Bibliographic Details
Published in:Chinese physics B 2024-11, Vol.33 (12), p.128503
Main Authors: Yu, Zhi-Meng, Yang, Xiao-Lei, Zhao, Xiao-Nan, Li, Yan-Jie, He, Shi-Kun, Wang, Ye-Wu
Format: Article
Language:English
Subjects:
back-side stress
magnetoresistive random access memory (MRAM)
metal-oxide-silicon field-effect transistor (MOSFET)
threshold voltage
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Summary:The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal–oxide–silicon field-effect transistors, especially on p-type devices. Herein, a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress. Through the deposition of tensile material on the back side, positive charges generated by silicon–hydrogen bond breakage were inhibited, resulting in a potential reduction in threshold voltage shift by up to 20%. In addition, it was found that the method could only relieve silicon–hydrogen bond breakage physically, thus failing to provide a complete cure. However, it holds significant potential for applications where additional thermal budget is undesired. Furthermore, it was also concluded that the method used in this work is irreversible, with its effect sustained to the chip package phase, and it ensures competitive reliability of the resulting magnetic tunnel junction devices.
ISSN:1674-1056
2058-3834
DOI:10.1088/1674-1056/ad7c2d