A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in...

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Bibliographic Details
Published in:Journal of semiconductors 2009-09, Vol.30 (9), p.66-69
Main Author: 袁凌 倪卫宁 郝志坤 石寅 李文昌
Format: Article
Language:English
Subjects:
DAC
ROM查找表
有效面积
电流模式
直接数字频率合成器
线性分段
设计过程
非线性
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Summary:This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.
ISSN:1674-4926
DOI:10.1088/1674-4926/30/9/095003