Cryogenic Analysis of Junctionless Nanowire MOSFET during Underlap in Lower Technology Nodes

This paper presents a cryogenic analysis of Junction less Under lapped Nanowire MOSFETs in lower technology nodes. The temperature dependent analysis is carried out to extract the DC figure of merits (FOMs) of the proposed nanowire MOSFET. The analysis is carried out to investigate the drain current...

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Bibliographic Details
Published in:Journal of physics. Conference series 2021-05, Vol.1879 (3), p.32124
Main Authors: Sasank, Tenneti Sai, Ganesh, Pochiraju Raja, Kumar, Nukala Pavan, Jena, Biswajit, Obaid, Ahmed J.
Format: Article
Language:English
Subjects:
Cryogenic
MOSFET
MOSFETs
Nano
Nanowires
Nodes
Physics
Resistance
Sub-threshold
Temperature dependence
Transconductance
Underlap
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Summary:This paper presents a cryogenic analysis of Junction less Under lapped Nanowire MOSFETs in lower technology nodes. The temperature dependent analysis is carried out to extract the DC figure of merits (FOMs) of the proposed nanowire MOSFET. The analysis is carried out to investigate the drain current associated with the device at different temperature. Further the analysis is extended with underlap length variation from source, drain and both sides. As the trans conductance plays a vital role in device performance estimation, so the analysis is further extended to calculate the transconductance for all the temperature variation and underlap length variation. With the introduction of gate metal under lapping, the sub-threshold behaviour of the proposed structure under different temperature is carried out extensively.
ISSN:1742-6588
1742-6596
DOI:10.1088/1742-6596/1879/3/032124