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A system-level method for hardening phase-locked loop to single-event effects

To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8...

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Bibliographic Details
Published in:Materials research express 2022-09, Vol.9 (9), p.96301
Main Authors: Liang, Bin, Xu, Xinyu, Yuan, Hengzhou, Chen, Jianjun, Luo, Deng, Chi, Yaqing, Sun, Hanhan
Format: Article
Language:English
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Summary:To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ∼ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and irradiated with heavy ions with a linear energy transfer between 1.9 and 65.6 MeV•cm 2 mg −1 . The proposed radiation-hardened PLL shows one order of single-event effects hardness level higher than the conventional PLL.
ISSN:2053-1591
2053-1591
DOI:10.1088/2053-1591/ac8f87