Modeling of jitter in bang-bang clock and data recovery circuits

Purpose - Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jit...

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Bibliographic Details
Published in:Compel 2013-01, Vol.32 (3), p.1151-1168
Main Authors: Adrang, Habib, Saleh Ghoreishi, Seyed
Format: Article
Language:English
Subjects:
Bandwidths
Binary systems
Circuits
Data recovery
Data transmission
Design
Jitter
Mathematical analysis
Mathematical models
Matlab
Nonlinear systems
Sensors
Simulation
Studies
Tolerances
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Summary:Purpose - Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized.Design methodology approach - The presented method is enough to be used for designing the BBCDR loop parameters.Findings - In this paper, jitter characteristics of the BBCDR are characterized. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The analysis is verified using behavioral simulations in MATLAB. Simulation results show that good conformance between analytical equations and simulation results.Originality value - The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero.
ISSN:0332-1649
2054-5606
DOI:10.1108/03321641311309067