Effects of the polarity of high-electric field stressing on power VDMOSFETs parameters

Purpose - The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems.Design methodology approach - A positive and a negative high-field stress are applied on the gate oxide of MOS devices and ele...

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Bibliographic Details
Published in:Microelectronics international 2010-01, Vol.27 (1), p.17-20
Main Authors: El Bitar, R, Salloum, G, Nsouli, B
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Compound structure devices
Electric fields
Electric, optical and optoelectronic circuits
Electrodes
Electronic circuits
Electronics
Electronics industry
Exact sciences and technology
Interfaces
Microelectronics
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Statistical analysis
Studies
Switching, multiplexing, switched capacity circuits
Transistors
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Summary:Purpose - The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems.Design methodology approach - A positive and a negative high-field stress are applied on the gate oxide of MOS devices and electrical characterization is performed after each period of stress, a comparison is presented.Findings - Compared results between the two types of stress show that certain doses of stress can increase the device speed. The underlying changes of the threshold voltage under these two types of stress are referred to as the variation of the gate oxide-trapped charge and interface trap densities.Originality value - This paper presents new and original experiments run over a number of metal-oxide semiconductor field effect transistor devices to compare the effects of the direction of the applied field on the degradation and the reliability of these structures.
ISSN:1356-5362
1758-812X
DOI:10.1108/13565361011009478