Design and analysis of a generalized architecture for reconfigurable m-ary tree structures

A generalized architecture is presented for reconfigurable m-ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990)...

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Bibliographic Details
Published in:IEEE transactions on computers 1992-11, Vol.41 (11), p.1465-1478
Main Authors: Srinivas, S., Biswas, N.N.
Format: Article
Language:English
Subjects:
Applied sciences
Communication switching
Computer architecture
Computer science
control theory
systems
Computer systems and distributed systems. User interface
Equations
Exact sciences and technology
Fault tolerance
Hardware
Network topology
Parallel architectures
Parallel processing
Resource management
Software
Tree data structures
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Summary:A generalized architecture is presented for reconfigurable m-ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with m/sup k/ processing elements or nodes (where k is any integer >1) is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.177316