Test scheduling and control for VLSI built-in self-test

The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potentia...

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Bibliographic Details
Published in:IEEE transactions on computers 1988-09, Vol.37 (9), p.1099-1109
Main Authors: Craig, G.L., Kine, C.R., Saluja, K.K.
Format: Article
Language:English
Subjects:
Applied sciences
Automatic testing
Built-in self-test
Circuit testing
Compressors
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Logic testing
Parallel processing
Pattern analysis
Scheduling algorithm
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Test pattern generators
Very large scale integration
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Summary:The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined, and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.2260