Short-channel pMOSTs in a high-resistivity silicon substrate. I. Analytical model

The behavior of short-channel pMOS transistors (2.5-25 mu m) in a high-resistivity silicon substrate (3-10 k Omega -cm), resulting from a 3- mu m CMOS process, especially optimized for the integration of totally depleted p-i-n type detectors and their readout electronics, is described both qualitati...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1992-10, Vol.39 (10), p.2268-2277
Main Authors: Vanstraelen, G., Simoen, E., Claeys, C., Declerck, G.J.
Format: Article
Language:English
Subjects:
Analytical models
CMOS process
CMOS technology
Detectors
Doping
MOSFETs
PIN photodiodes
Silicon
Superconducting device noise
Voltage
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Summary:The behavior of short-channel pMOS transistors (2.5-25 mu m) in a high-resistivity silicon substrate (3-10 k Omega -cm), resulting from a 3- mu m CMOS process, especially optimized for the integration of totally depleted p-i-n type detectors and their readout electronics, is described both qualitatively and quantitatively. Their behavior is examined both in the off-region, where bulk punchthrough and space-charge limitations prevail, and in the on-region. Simulations and experimental data show that these transistors exhibit a second linear region, referred to as quasi-linear region, instead of the normal saturation region.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.158798