A novel, shallow-trench-isolated, planar, N+SAG FAMOS transistor for high-density nonvolatile memories

• Published in: IEEE transactions on electron devices 1988-12, Vol.35 (12), p.2437
• Main Authors: Esquivel, A.L., Mitchell, A.T., Huffman, C., Paterson, J.L., Tigelaar, H.L., Riemenschneider, B.R.
• Format: Article
• Language: English
• Subjects: Anisotropic magnetoresistance; Chemical vapor deposition; EPROM; Etching; Fabrication; MOSFETs; Nonvolatile memory; PROM; Silicon; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.8852

The authors report the fabrication, for the first time, of a shallow-trench isolated (less than 1 mu m deep) planarized, floating-gate avalanche injection MOS (FAMOS) transistor with n/sup +/ bitlines self-aligned to gate (n/sup +/ SAG). Key to the planar process is the self-alignment of the buried n/sup +/ diffusions (bitlines) to the floating gate of the FAMOS transistor and the deposition over these diffusions of a low-temperature, conformal CVD (chemical vapor deposition) oxide. An oxide-resist etchback process was used to planarize the buried n/sup +/ CVD oxide. Trench etching was done immediately after definition of the stacked polysilicon gates. Using an anisotropic etch for single-crystal silicon, trenches with a 0.75 mu m depth were made in the bitline isolation areas of the planar devices. The trenches were then refilled with thermal and LPCVD (liquid-phase CVD) SiO/sub 2/. Characterization of the planar EPROM (erasable programmable read-only memory) cell shows that the shallow trench between bitlines has improved their isolation characteristics. An increase in programming efficiency of as much as 30% at a pulse width of 1 ms was observed in the case of the shallow-trench-isolated FAMOS. Additional data indicate the possibility of programming the trench isolated cell at drain voltages lower than the present 12.5 V, thus reducing high voltage requirements.< >