Interfacing slave designs to FASTBUS: practical experience

The authors have designed a number of FASTBUS slave modules, using a standard interface circuit and standard design-verification tools based on computer-aided-engineering (CAE) techniques. They describe the standard interface and the design and verification methodology. The interface logic for FASTB...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 1988-02, Vol.35 (1), p.288-291
Main Authors: Downing, R.W., Hoeflich, J.J., Simaitis, V.J., Pregernig, L.F.
Format: Article
Language:English
Subjects:
Application software
Circuits
Computer aided engineering
Costs
Fastbus
Latches
Logic design
Protocols
Registers
Very large scale integration
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Description
Summary:The authors have designed a number of FASTBUS slave modules, using a standard interface circuit and standard design-verification tools based on computer-aided-engineering (CAE) techniques. They describe the standard interface and the design and verification methodology. The interface logic for FASTBUS slaves is divided into three blocks: the slave control logic, slave address/data logic, and slave support logic. The control logic is a hybrid chip that handles the protocol portion of the interface. The slave address/data logic includes the functions performed by the address/data interface chip and additional data-path related components, i.e. registers, buffers, and level shifters. The support logic is additional logic necessary to glue the other blocks and application logic together.< >
ISSN:0018-9499
1558-1578
DOI:10.1109/23.12726