A massively parallel track-finding system for the LEVEL 2 trigger in the CLAS detector at CEBAF

The track segment finding subsystem of the LEVEL 2 trigger in the CLAS detector has been designed and prototyped. Track segments will be found in the 35,076 wires of the drift chambers using a massively parallel array of 768 Xilinx XC-4005 FPGA's. These FPGAs are located on daughter cards attac...

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Bibliographic Details
Published in:IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) 1994-02, Vol.41 (1), p.267-273
Main Authors: Doughty, D.C., Collins, P., Lemon, S., Bonneau, P.
Format: Article
Language:English
Subjects:
430303 > Particle Accelerators-- Experimental Facilities & Equipment
ACCELERATORS
CEBAF ACCELERATOR
CHERENKOV COUNTERS
Coils
COMPUTERS
DATA ACQUISITION SYSTEMS
DESIGN
DRIFT CHAMBERS
Electron beams
ELECTRONIC CIRCUITS
INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
LINEAR ACCELERATORS
Magnetic field measurement
MAGNETIC SPECTROMETERS
MEASURING INSTRUMENTS
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
MULTIWIRE PROPORTIONAL CHAMBERS
PARTICLE ACCELERATORS
Particle measurements
Particle tracking
PARTICLE TRACKS
PROGRAMMING
PROPORTIONAL COUNTERS
PULSE CIRCUITS
RADIATION DETECTORS
SCINTILLATION COUNTERS
SHOWER COUNTERS
Solid scintillation detectors
SPECTROMETERS 440104 > Radiation Instrumentation-- High Energy Physics Instrumentation
Spectroscopy
Toroidal magnetic fields
Trajectory
TRIGGER CIRCUITS
Wires
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Summary:The track segment finding subsystem of the LEVEL 2 trigger in the CLAS detector has been designed and prototyped. Track segments will be found in the 35,076 wires of the drift chambers using a massively parallel array of 768 Xilinx XC-4005 FPGA's. These FPGAs are located on daughter cards attached to the front-end boards distributed around the detector. Each chip is responsible for finding tracks passing through a 4/spl times/6 slice of an axial superlayer, and reports two 'segment found' bits, one for each pair of cells. The algorithm used finds segments even when one or two layers or cells along the track is missing (this number is programmable), while being highly resistant to false segments arising from noise hits. Adjacent chips share data to find tracks crossing cell and board boundaries. For maximum speed, fully combinatorial logic is used inside each chip, with the result that all segments in the detector are found within 150 ns. Segment collection boards gather track segments from each axial superlayer and pass them via a high speed link to the segment linking subsystem in an additional 400 ns for typical events. The Xilinx chips are ram-based and therefore reprogrammable, allowing for future upgrades and algorithm enhancements.< >
ISSN:0018-9499
1558-1578
DOI:10.1109/23.281502