Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during tr...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2000-12, Vol.47 (6), p.2675-2681
Main Authors: Jih-Jong Wang, Katz, R.B., Dhaoui, F., McCollum, J.L., Wong, W., Cronquist, B.E., Lambertson, R.T., Hamdy, E., Kleyner, I., Parker, W.
Format: Article
Language:English
Subjects:
Circuit simulation
Circuit testing
Circuits
Clocks
Devices
DH-HEMTs
Field programmable gate arrays
Hardness
Optimization methods
Programmable logic arrays
Simulation
Single event upset
Soft errors
SPICE
Strikes
Ultra large scale integration
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Summary:Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET/sub th/. The difference between LET/sub th/ at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.
ISSN:0018-9499
1558-1578
DOI:10.1109/23.903825