The evolution of instruction sequencing

The three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence...

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 1991-04, Vol.24 (4), p.5-15
Main Authors: Krick, R.F., Dollas, A.
Format: Article
Language:English
Subjects:
Bandwidth
Bipolar transistors
Context modeling
Interleaved codes
Magnetic cores
Random access memory
Semiconductor memory
System performance
Tellurium
Terminology
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Summary:The three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence of the available technology on the minimum time required for each of these phases and the resulting design decisions. Rather than absolute system performance. the interrelationship of these critical parameters is examined. Memory bandwidth, instruction buffers, caches, and the impact of reduced-instruction-set computers (RISCs) are discussed. Recent innovations are described, and the options and constraints that designers face with respect to future developments are evaluated.< >
ISSN:0018-9162
1558-0814
DOI:10.1109/2.76259