A parallel genetic algorithm for performance-driven VLSI routing

This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of n...

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Bibliographic Details
Published in:IEEE transactions on evolutionary computation 1997-04, Vol.1 (1), p.29-39
Main Author: Lienig, J.
Format: Article
Language:English
Subjects:
Capacitance
Concurrent computing
Crosstalk
Delay
Electronics packaging
Genetic algorithms
Integrated circuit interconnections
Routing
Very large scale integration
Workstations
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Summary:This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). The parallel approach is shown to consistently perform better than a sequential genetic algorithm when applied to these routing problems. An extensive investigation of the parameters of the algorithm yields routing results that are qualitatively better or as good as the best published results. In addition, the algorithm is able to significantly reduce the occurrence of crosstalk.
ISSN:1089-778X
1941-0026
DOI:10.1109/4235.585890