Analysis and design of latch-controlled synchronous digital circuits

The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP)...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1992-03, Vol.11 (3), p.322-333
Main Authors: Sakallah, K.A., Mudge, T.N., Olukotun, O.A.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit analysis
Circuit topology
Clocks
Design. Technologies. Operation analysis. Testing
Digital circuits
Electronics
Exact sciences and technology
Inspection
Integrated circuits
Latches
Linear programming
Logic
Propagation delay
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
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Summary:The authors present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. It is shown that the constraints are mildly nonlinear. The equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem is proved. A LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multiphase overlapped clocks is presented. The formulation and an initial implementation of the algorithm on some example circuits are illustrated.< >
ISSN:0278-0070
1937-4151
DOI:10.1109/43.124419