Timing optimization by gate resizing and critical path identification

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1995-02, Vol.14 (2), p.201-217
• Main Authors: Fang, Chen-Liang, Jone, Wen-Ben
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit simulation; Computer science; Digital circuits; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Fabrication; Hardware; Optimization methods; Propagation delay; Semiconductor device manufacture; Theoretical study. Circuits analysis and design; Timing; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.370424

Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, use of a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM, called /spl tau/PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitively reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing.< >