Transistor sizing for low power CMOS circuits

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the powe...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1996-06, Vol.15 (6), p.665-671
Main Authors: Borah, M., Owens, R.M., Irwin, M.J.
Format: Article
Language:English
Subjects:
Analytical models
Circuit simulation
Delay
Energy consumption
Power dissipation
SPICE
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Summary:A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the power dissipation of a circuit in terms of the transistor size is derived which includes both the capacitive and the short circuit power dissipation. SPICE circuit simulation results are presented to confirm the correctness of the analytical model. Based on the intuitions drawn from the analytical model, heuristics for initial transistor sizing on critical and noncritical paths for minimum power consumption are developed. Further, fast heuristics to perform transistor sizing in CMOS circuits for minimizing power consumption while meeting the given delay constraints are presented.
ISSN:0278-0070
1937-4151
DOI:10.1109/43.503935