Analysis of propagation delays in high-speed VLSI circuits using a distributed line model

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1990-08, Vol.9 (8), p.821-826
• Main Authors: Passlack, M., Uhle, M., Elschner, H.
• Format: Article
• Language: English
• Subjects: Applied sciences; Boundary conditions; Circuit simulation; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Gallium arsenide; Integrated circuit interconnections; Integrated circuits; MESFET circuits; Propagation delay; Scattering parameters; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Superconducting logic circuits; Transconductance; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.57789

A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures.< >