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Analysis of propagation delays in high-speed VLSI circuits using a distributed line model
A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-spee...
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Published in: | IEEE transactions on computer-aided design of integrated circuits and systems 1990-08, Vol.9 (8), p.821-826 |
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container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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creator | Passlack, M. Uhle, M. Elschner, H. |
description | A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures.< > |
doi_str_mv | 10.1109/43.57789 |
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Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures.< ></description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.57789</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Boundary conditions ; Circuit simulation ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Gallium arsenide ; Integrated circuit interconnections ; Integrated circuits ; MESFET circuits ; Propagation delay ; Scattering parameters ; Semiconductor electronics. Microelectronics. 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Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures.< ></description><subject>Applied sciences</subject><subject>Boundary conditions</subject><subject>Circuit simulation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gallium arsenide</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>MESFET circuits</subject><subject>Propagation delay</subject><subject>Scattering parameters</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gallium arsenide</topic><topic>Integrated circuit interconnections</topic><topic>Integrated circuits</topic><topic>MESFET circuits</topic><topic>Propagation delay</topic><topic>Scattering parameters</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.57789</doi><tpages>6</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Journals |
subjects | Applied sciences Boundary conditions Circuit simulation Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Gallium arsenide Integrated circuit interconnections Integrated circuits MESFET circuits Propagation delay Scattering parameters Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Superconducting logic circuits Transconductance Very large scale integration |
title | Analysis of propagation delays in high-speed VLSI circuits using a distributed line model |
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