A recommended error control architecture for ATM networks with wireless links

This paper provides performance results through analysis and simulation for key error control problems encountered in using wireless links to transport asynchronous transfer mode (ATM) cells. Problems considered include the forward-error correction (FEC) and interleaving at the physical layer, the i...

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Bibliographic Details
Published in:IEEE journal on selected areas in communications 1997-01, Vol.15 (1), p.16-28
Main Authors: Cain, J.B., McGregor, D.N.
Format: Article
Language:English
Subjects:
Analytical models
Asynchronous transfer mode
Automatic control
Automatic repeat request
Error correction
Forward error correction
Interleaved codes
Performance analysis
Physical layer
Transport protocols
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Summary:This paper provides performance results through analysis and simulation for key error control problems encountered in using wireless links to transport asynchronous transfer mode (ATM) cells. Problems considered include the forward-error correction (FEC) and interleaving at the physical layer, the impact of wireless links on the ATM cell header-error control (HEC) sand cell delineation (CD) functions, the application of data link automatic repeat-request (ARQ) for traffic requiring reliable transport, and the impact of the choice of end-to-end ARQ protocol for reliable service. We conclude that it is very important to make the physical layer as SONET-like as possible through the use of powerful FEC, interleaving, and ARQ. These additional error control measures are especially necessary for disturbed channels because of the degrading effects of the channel on higher-layer functions. A recommended error control architecture is given with tradeoffs.
ISSN:0733-8716
1558-0008
DOI:10.1109/49.553675