A VLSI chip set for a large-scale parallel inference machine: PIM/m

• Published in: IEEE journal of solid-state circuits 1993-03, Vol.28 (3), p.344-351
• Main Authors: Machida, H., Ando, H., Yasuda, K., Furutani, K., Yamashita, Y., Nakashima, H., Takeda, Y., Nakajima, K., Sakao, M., Nakaya, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Artificial intelligence; Cache memory; CMOS technology; Concurrent computing; Electronics; Exact sciences and technology; Information processing; Integrated circuits; Integrated circuits by function (including memories and processors); Laboratories; Large-scale systems; Logic programming; Mesh networks; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Very large scale integration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.210002

The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called 'trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 mu m double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 mu m double-metal CMOS technology. A cell-based design method is used to reduce the layout design time.< >