Comments on the optimum CMOS tapered buffer problem

• Published in: IEEE journal of solid-state circuits 1994-02, Vol.29 (2), p.155-158
• Main Authors: Hedenstierna, N., Jeppson, K.O.
• Format: Article
• Language: English
• Subjects: Capacitance; Circuit simulation; Clocks; Driver circuits; Equations; Inverters; Propagation delay; Solid state circuits; SPICE; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.272124

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent "short-circuit" current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the "short-circuit" current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations.< >