Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder

The adder is intended to be used as a building block in the design of more complex circuits and systems using very large scale integration (VLSI). An efficient approach to error detection has been selected through extensive comparisons of several methods that use hardware, time, and hybrid redundanc...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1988-02, Vol.23 (1), p.208-215
Main Authors: Johnson, B.W., Aylor, J.H., Hana, H.H.
Format: Article
Language:English
Subjects:
Adders
Applied sciences
Delay
Electronics
Exact sciences and technology
Fault detection
Fault tolerance
Fault tolerant systems
Hardware
Integrated circuits
Libraries
Process design
Redundancy
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Very large scale integration
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Summary:The adder is intended to be used as a building block in the design of more complex circuits and systems using very large scale integration (VLSI). An efficient approach to error detection has been selected through extensive comparisons of several methods that use hardware, time, and hybrid redundancy. Simulation and analysis results are presented to illustrate the adder's timing characteristics, hardware requirements, and error-detection capabilities. One novel feature of the analysis is the introduction of error latency as a means of comparing the error-detection capabilities of several alternative approaches.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.281