A multiplexer-based architecture for high-density, low-power gate arrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to cr...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1995-04, Vol.30 (4), p.392-396
Main Authors: Landers, R.J., Mahant-Shetti, S.S., Lemonds, C.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Degradation
Delay
Driver circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Feeds
Instruments
Libraries
Multiplexing
Power dissipation
Product design
SPICE
Switching, multiplexing, switched capacity circuits
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Summary:This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.375958