High speed, high linearity CMOS buffer amplifier

A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequenc...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1996-02, Vol.31 (2), p.255-258
Main Authors: Saether, T., Chung-Chih Hung, Zheng Qi, Ismail, M., Aaserud, O.
Format: Article
Language:English
Subjects:
Capacitors
CMOS technology
Frequency
Impedance
Linearity
Low-noise amplifiers
Rail to rail amplifiers
Rail to rail outputs
Testing
Voltage
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Summary:A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.488003