High speed, high linearity CMOS buffer amplifier

A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequenc...

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Published in:IEEE journal of solid-state circuits 1996-02, Vol.31 (2), p.255-258
Main Authors: Saether, T., Chung-Chih Hung, Zheng Qi, Ismail, M., Aaserud, O.
Format: Article
Language:English
Subjects:
Capacitors
CMOS technology
Frequency
Impedance
Linearity
Low-noise amplifiers
Rail to rail amplifiers
Rail to rail outputs
Testing
Voltage
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cited_by cdi_FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3
cites cdi_FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3
container_end_page 258
container_issue 2
container_start_page 255
container_title IEEE journal of solid-state circuits
container_volume 31
creator Saether, T.
Chung-Chih Hung
Zheng Qi
Ismail, M.
Aaserud, O.
description A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.
doi_str_mv 10.1109/4.488003
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_4_488003</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>488003</ieee_id><sourcerecordid>28327783</sourcerecordid><originalsourceid>FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3</originalsourceid><addsrcrecordid>eNo90DFPwzAQBWALgUQpSMxMmRADKT47iS8jqoAiFXUAJDbLic_UKG2DnQz996RKxXR3uk9veIxdA58B8PIhm2WInMsTNoE8xxSU_DplE84B01Jwfs4uYvwZzixDmDC-8N_rJLZE9j5ZH_bGb8kE3-2T-dvqPal65ygkZtM23nkKl-zMmSbS1XFO2efz08d8kS5XL6_zx2VaC5V3KXGUCkWhuCBboSFEZ4VBoZSzZQbS1rktQQqowDqFCHVRlUJRIZzA2skpux1z27D77Sl2euNjTU1jtrTroxYohyyUA7wbYR12MQZyug1-Y8JeA9eHSnSmx0oGejNST0T_7Pj8A2jUWZ8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28327783</pqid></control><display><type>article</type><title>High speed, high linearity CMOS buffer amplifier</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Saether, T. ; Chung-Chih Hung ; Zheng Qi ; Ismail, M. ; Aaserud, O.</creator><creatorcontrib>Saether, T. ; Chung-Chih Hung ; Zheng Qi ; Ismail, M. ; Aaserud, O.</creatorcontrib><description>A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.488003</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitors ; CMOS technology ; Frequency ; Impedance ; Linearity ; Low-noise amplifiers ; Rail to rail amplifiers ; Rail to rail outputs ; Testing ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1996-02, Vol.31 (2), p.255-258</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3</citedby><cites>FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/488003$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Saether, T.</creatorcontrib><creatorcontrib>Chung-Chih Hung</creatorcontrib><creatorcontrib>Zheng Qi</creatorcontrib><creatorcontrib>Ismail, M.</creatorcontrib><creatorcontrib>Aaserud, O.</creatorcontrib><title>High speed, high linearity CMOS buffer amplifier</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.</description><subject>Capacitors</subject><subject>CMOS technology</subject><subject>Frequency</subject><subject>Impedance</subject><subject>Linearity</subject><subject>Low-noise amplifiers</subject><subject>Rail to rail amplifiers</subject><subject>Rail to rail outputs</subject><subject>Testing</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNo90DFPwzAQBWALgUQpSMxMmRADKT47iS8jqoAiFXUAJDbLic_UKG2DnQz996RKxXR3uk9veIxdA58B8PIhm2WInMsTNoE8xxSU_DplE84B01Jwfs4uYvwZzixDmDC-8N_rJLZE9j5ZH_bGb8kE3-2T-dvqPal65ygkZtM23nkKl-zMmSbS1XFO2efz08d8kS5XL6_zx2VaC5V3KXGUCkWhuCBboSFEZ4VBoZSzZQbS1rktQQqowDqFCHVRlUJRIZzA2skpux1z27D77Sl2euNjTU1jtrTroxYohyyUA7wbYR12MQZyug1-Y8JeA9eHSnSmx0oGejNST0T_7Pj8A2jUWZ8</recordid><startdate>199602</startdate><enddate>199602</enddate><creator>Saether, T.</creator><creator>Chung-Chih Hung</creator><creator>Zheng Qi</creator><creator>Ismail, M.</creator><creator>Aaserud, O.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199602</creationdate><title>High speed, high linearity CMOS buffer amplifier</title><author>Saether, T. ; Chung-Chih Hung ; Zheng Qi ; Ismail, M. ; Aaserud, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Capacitors</topic><topic>CMOS technology</topic><topic>Frequency</topic><topic>Impedance</topic><topic>Linearity</topic><topic>Low-noise amplifiers</topic><topic>Rail to rail amplifiers</topic><topic>Rail to rail outputs</topic><topic>Testing</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Saether, T.</creatorcontrib><creatorcontrib>Chung-Chih Hung</creatorcontrib><creatorcontrib>Zheng Qi</creatorcontrib><creatorcontrib>Ismail, M.</creatorcontrib><creatorcontrib>Aaserud, O.</creatorcontrib><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Saether, T.</au><au>Chung-Chih Hung</au><au>Zheng Qi</au><au>Ismail, M.</au><au>Aaserud, O.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>High speed, high linearity CMOS buffer amplifier</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1996-02</date><risdate>1996</risdate><volume>31</volume><issue>2</issue><spage>255</spage><epage>258</epage><pages>255-258</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.</abstract><pub>IEEE</pub><doi>10.1109/4.488003</doi><tpages>4</tpages></addata></record>
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language eng
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source IEEE Electronic Library (IEL) Journals
subjects Capacitors
CMOS technology
Frequency
Impedance
Linearity
Low-noise amplifiers
Rail to rail amplifiers
Rail to rail outputs
Testing
Voltage
title High speed, high linearity CMOS buffer amplifier
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T18%3A04%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=High%20speed,%20high%20linearity%20CMOS%20buffer%20amplifier&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Saether,%20T.&rft.date=1996-02&rft.volume=31&rft.issue=2&rft.spage=255&rft.epage=258&rft.pages=255-258&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.488003&rft_dat=%3Cproquest_cross%3E28327783%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c275t-e0837826702edb8ae88fd2a8277fd9413dc5d91321b1df7881c6b927e62f28cf3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=28327783&rft_id=info:pmid/&rft_ieee_id=488003&rfr_iscdi=true