A 12-ns ECL I/O 256 K1-bit SRAM using a 1- mu m BiCMOS technology

An ECL (emitter-coupled-logic) I/O 256K*1-bit SRAM (static random-access memory) has been developed using a 1- mu m BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8- mu m CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1988-10, Vol.23 (5), p.1048-1053
Main Authors: Kertis, R.A., Smith, D.D., Bowman, T.L.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
Bipolar transistors
Circuit simulation
CMOS memory circuits
CMOS process
CMOS technology
Decoding
Minimization methods
MOS devices
Random access memory
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Summary:An ECL (emitter-coupled-logic) I/O 256K*1-bit SRAM (static random-access memory) has been developed using a 1- mu m BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8- mu m CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.5923