Low-power dynamic termination scheme using NMOS diode clamping

An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (V/sub th/) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open te...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1999-08, Vol.34 (8), p.1171-1175
Main Authors: Shin, Dong-Ho, Lee, Young-Min, Kim, Kyu-Hyoun, Lee, Kwyro
Format: Article
Language:English
Subjects:
Circuit simulation
Circuits
Clamping
Clamps
Diodes
Dynamics
Electrostatic discharge
High speed
Humans
Immune system
Integrated circuit interconnections
Interconnection
MOS devices
Nanostructure
Pulse circuits
Threshold voltage
Voltage
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Summary:An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (V/sub th/) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open termination, the magnitudes of both overshoot and undershoot for nanosecond-range input pulses are typically less than /spl sim/15% of supply voltage (V/sub cc/=/sub 3.3/ V) with the same order of magnitude in power saving. Finally, the NDCT is found to be very immune to electrostatic discharge, guaranteeing more than 3000 V for a human body model. Our results demonstrate the potentiality of NDCT as a high-speed interconnection scheme.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.777116