Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive load...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2000-02, Vol.35 (2), p.221-230
Main Authors: Ka Nang Leung, Mok, P.K.T., Wing-Hung Ki, Sin, J.K.O.
Format: Article
Language:English
Subjects:
Amplifiers
Bandwidth
Capacitors
Circuit topology
CMOS
CMOS process
Compensation
Driving
Energy consumption
Frequency
Power amplifiers
Power consumption
Power supplies
Settling
Transient response
Transient responses
Voltage
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Summary:A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.823447