Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

A universal-V/sub dd/ 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-/spl mu/m enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V. Its operating frequency and power are from 120 MHz and 1.7 mW at 0.6...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1738-1744
Main Authors: Osada, K., Jinuk Luke Shin, Khan, M., Liou, Y., Wang, K., Shoji, K., Kuroda, K., Ikeda, S., Ishibashi, K.
Format: Article
Language:English
Subjects:
Circuits
CMOS technology
Delay lines
Frequency
Microprocessors
Power dissipation
Random access memory
SRAM chips
Testing
Threshold voltage
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Summary:A universal-V/sub dd/ 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-/spl mu/m enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V. Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V. The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.962296