Re-evaluation of the benefits of postoxidation annealing on sub-100 /spl Aring/ gate oxide quality

• Published in: IEEE electron device letters 1996-06, Vol.17 (6), p.282-284, Article 282
• Main Authors: Ajuria, S.A., Maiti, B., Tobin, P.J., Mele, T.C.
• Format: Article
• Language: English
• Subjects: Dielectric substrates; Electron traps; MOS capacitors; MOSFET circuits; Oxidation; Rapid thermal annealing; Rapid thermal processing; Silicon; Temperature; Voltage
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.496458

The effects of postoxidation annealing (POA) on thin gate oxide quality are evaluated in two different MOS integration schemes. One scheme involves a high temperature backend step consisting of a 20-s 1065/spl deg/C rapid thermal anneal after gate polysilicon deposition. The second involves a much lower temperature backend step consisting of a 20-s 800-850/spl deg/C rapid thermal anneal. It is demonstrated that although the POA significantly improves dielectric properties such as charge to breakdown and interface hardness at very low backend temperatures, it does little to improve such properties at high backend temperatures. Given that typical semiconductor processes often include thermal steps that exceed gate oxidation temperatures, it may be possible to eliminate POA with no adverse effects. Eliminating POA can in turn reduce processing time and further reduce total thermal budget.