Solder wetting in a wafer-level flip chip assembly

• Published in: IEEE transactions on electronics packaging manufacturing 2001-07, Vol.24 (3), p.154-159
• Main Authors: Jicun Lu, Busch, S.C., Baldwin, D.F.
• Format: Article
• Language: English
• Subjects: Assembly; Chips; Collapse; Confining; Flip chip; Metallization; Metallizing; Monitoring; Outgassing; Packaging; Real time systems; Solders; Studies; Surface-mount technology; Temperature; Throughput; Wafer scale integration; Wetting
• ISSN: 1521-334X; 1558-0822
• DOI: 10.1109/6104.956800

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated.