A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorith...

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Bibliographic Details
Published in:IEEE access 2019, Vol.7, p.125240-125252
Main Authors: Tripathi, Jai Narayan, Illikkal, Muhammed Suhail, Shrimali, Hitesh, Achar, Ramachandra
Format: Article
Language:English
Subjects:
Algorithms
Buffers
chain of inverters
Chains
clock-network
CMOS
CMOS inverter
delay-line
Harmonic analysis
I/O
Inverters
Jitter
Modelling
Power supplies
Power supply
power supply induced jitter
power supply noise
tapered buffer
time interval error
Timing
Transfer functions
Transistors
Vibration
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Summary:This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2019.2937922