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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers
This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorith...
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| Published in: | IEEE access 2019, Vol.7, p.125240-125252 |
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| Main Authors: | , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c408t-b7807abfc205819913a140ae5cb2d60a5dcb33f782487479aacdf98affc1cf663 |
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| cites | cdi_FETCH-LOGICAL-c408t-b7807abfc205819913a140ae5cb2d60a5dcb33f782487479aacdf98affc1cf663 |
| container_end_page | 125252 |
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| container_start_page | 125240 |
| container_title | IEEE access |
| container_volume | 7 |
| creator | Tripathi, Jai Narayan Illikkal, Muhammed Suhail Shrimali, Hitesh Achar, Ramachandra |
| description | This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. |
| doi_str_mv | 10.1109/ACCESS.2019.2937922 |
| format | article |
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| fulltext | fulltext |
| identifier | ISSN: 2169-3536 |
| ispartof | IEEE access, 2019, Vol.7, p.125240-125252 |
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| source | IEEE Open Access Journals |
| subjects | Algorithms Buffers chain of inverters Chains clock-network CMOS CMOS inverter delay-line Harmonic analysis I/O Inverters Jitter Modelling Power supplies Power supply power supply induced jitter power supply noise tapered buffer time interval error Timing Transfer functions Transistors Vibration |
| title | A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers |
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