Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

This article recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques prop...

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Bibliographic Details
Published in:IEEE access 2021, Vol.9, p.14816-14835
Main Authors: Teh, Eng Keong, Zawawi, Mohamad Adzhar Md, Mohamed, Mohamed Fauzi Packeer, Isa, Nor Ashidi Mat
Format: Article
Language:English
Subjects:
Algorithms
artificial intelligence
clock distribution
Clocks
Complex systems
deep sub-micrometer
Heuristic methods
hybrid meta-heuristic
Jitter
Network topologies
Network topology
Routing
System on chip
System-on-a-chip (SoC)
Timing
Topology
Uncertainty
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Summary:This article recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques proposed in the prior arts are no longer practical or enough. With that, we introduce a flexible FC Clock network topology and a synthesis algorithm that utilize a hybrid meta-heuristic technique to search for near optimum solution in shorter turn-around time. Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3053052