New Memory Architecture for Rolling Shutter Wide Dynamic Range CMOS Imagers

In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, al...

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Bibliographic Details
Published in:IEEE sensors journal 2012-04, Vol.12 (4), p.767-772
Main Authors: Sandhu, Tejinder Singh, Pecht, Orly Yadid
Format: Article
Language:English
Subjects:
Arrays
Decoding
Dynamic range
Leakage power reduction
Memory architecture
Memory management
memory size reduction
new memory architecture
Pixel
wide dynamic range (WDR) CMOS active pixel sensors (APSs)
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Summary:In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, allowing a pixel to independently set its integration period as per its ambient light level. Traditionally these WDR bits are stored in a dedicated memory location for every pixel. We propose a new memory architecture which, in principal, is similar to time division multiplexing, such that it achieves memory size reduction by sharing a single memory location among a number of pixels as a function of time. The proposed architecture is ideally suited for rolling shutter APS, where each row is processed sequentially in time. Compared to a commonly used memory design, the proposed architecture becomes increasingly efficient as the pixel count increases, resulting in momentous savings in memory chip area and leakage power consumption. For a pixel array of 128 * 128, only 14.2% of the commonly used memory bits are required, when using 7 WDR bits per pixel. This requirement reduces to 8.3% of the commonly used memory bits for a pixel array size of 4096 * 4096, rendering the purposed architecture particularly efficient for larger arrays. The savings in leakage power will track the corresponding savings in memory size and area especially for newer technologies. The purposed concept has been verified in design and simulation for a 128 * 128 pixel array, fabricated in 180 nm technology.
ISSN:1530-437X
1558-1748
DOI:10.1109/JSEN.2011.2132702