Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1978-04, Vol.13 (2), p.218-224
Main Authors: Ieda, N., Ohmori, Y., Takeya, K., Yano, T.
Format: Article
Language:English
Subjects:
Circuits
Clocks
Fabrication
Large scale integration
MOSFETs
Multiplexing
Power dissipation
Random access memory
Read-write memory
Threshold voltage
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Summary:The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1978.1051022