Effects of gate geometry on propagation delay of integrated injection logic (I/sup 2/L)

The effects of gate geometry on the propagation delay have been investigated for I/SUP 2/L gates with a self-aligned double-diffusion injector (S/SUP 2/L). To improve the switching speed of the I/SUP 2/L gate, the stored charge in the upside-down operated n-p-n transistor in the gate should be minim...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1978-04, Vol.13 (2), p.225-230
Main Authors: Shinozaki, S., Shinada, K., Miyamoto, J.
Format: Article
Language:English
Subjects:
Analytical models
Delay effects
Fabrication
Geometry
Impurities
Logic
Propagation delay
Research and development
Ring oscillators
Substrates
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Summary:The effects of gate geometry on the propagation delay have been investigated for I/SUP 2/L gates with a self-aligned double-diffusion injector (S/SUP 2/L). To improve the switching speed of the I/SUP 2/L gate, the stored charge in the upside-down operated n-p-n transistor in the gate should be minimized. Following this principle, one can straightforwardly find that the reduction of the stored charges in the internal n-p-n base region and in the lateral p-n-p base region is the step to be taken for the further improvement of the speed. This can be realized by simply contracting the geometry of the gate. The minimum delay time realized in the gate was 3.2 ns/gate. Assuming that capabilities of processing the devices with 1-/spl mu/m accuracy become available, it is predicted that 1 ns/gate delay time can be realized with an improved S/SUP 2/L gate.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1978.1051023