On the logic delay in MOS LSI static NOR designs

Conventional definitions of logic block delay are reviewed and a preferred one is proposed, on a statistical basis, for the static NOR circuits in an LSI MOSFET technology. According to this definition, the delay is based on the actual circuit thresholds depends minimally on the input transition rat...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 1979-08, Vol.14 (4), p.716-723
Main Author: Puri, Y.
Format: Article
Language:English
Subjects:
Circuit simulation
Circuit testing
Computational modeling
Delay
FETs
Large scale integration
Logic circuits
Logic design
Logic testing
Production
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Conventional definitions of logic block delay are reviewed and a preferred one is proposed, on a statistical basis, for the static NOR circuits in an LSI MOSFET technology. According to this definition, the delay is based on the actual circuit thresholds depends minimally on the input transition rate and is always positive. Moreover critical pulsewidths are given directly in terms of block delays. Using this definition, the block and path delay statistics are derived for use in CAD simulation of chip logic and performance in some limited sense. Finally, examples are given illustrating the use of delay definition in chip delay and pulsewidth.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1979.1051249