A high-speed Hi-CMOSII 4K static RAM

Using advanced high-performance CMOS (Hi-CMOSII) technology and a high-speed circuit technique, a fully static 4096-word by one-bit RAM with typical address access time of 18 ns and power dissipation of 150 mW has been designed. The power-access-time product realized by the design is almost an order...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1981-10, Vol.16 (5), p.449-453
Main Authors: Minato, O., Masuhara, T., Sasaki, T., Sakai, Y., Yoshizaki, K.
Format: Article
Language:English
Subjects:
CMOS technology
Coupling circuits
High speed integrated circuits
Integrated circuit technology
MOS devices
MOSFETs
Power dissipation
Transistors
Very large scale integration
Virtual manufacturing
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Summary:Using advanced high-performance CMOS (Hi-CMOSII) technology and a high-speed circuit technique, a fully static 4096-word by one-bit RAM with typical address access time of 18 ns and power dissipation of 150 mW has been designed. The power-access-time product realized by the design is almost an order of magnitude better than existing NMOS 4K static RAMs. Moreover, to produce low-cost high-density static RAMs, a new redundancy technique utilizing laser shorting of intrinsic polysilicon is proposed.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1981.1051621